| To ensure that
flip-flops change in synchronism with other parts of the circuit, they
are not allowed to change state until they receive a CLOCK PULSE.
SET and RESET cannot affect the outputs unless the clock pulse is high. In the TIMING DIAGRAM below, at A, SET is HIGH but the CLOCK is LOW, so there is no change in the outputs. At B, SET is
still HIGH, and CLOCK is HIGH.
At C, the CLOCK
is HIGH and RESET has gone HIGH.
At D, the
CLOCK is HIGH but SET is LOW.
At E, CLOCK and
SET are both HIGH.
|
