The counter output can be set to zero by pulsing the reset line low.

The count then increments on each clock pulse until it reaches 1001 (decimal 9).

When it increments to 1010 (decimal 10)  both inputs of the nand gate go high.

The result is that the nand output goes low, and resets the counter to zero.

D going low can be a CARRY OUT signal, indicating that there has been a count of ten.